Principal Engineer - Design Verification

Job Responsibilities

• Drive Verification R&D team driving technical execution and best in class methodologies used in the design of advanced microcontrollers and microprocessors.
• Work closely with system architects to understand high level specifications to be able to verify them.
• Work with various EDA vendors to deploy next generation tools
• Build strong collaboration with other R&D teams such as RTL, DFT, digital IP, PD, Design Enablement, Emulation, and Validation to achieve project milestones
• Promote continuous improvement to design techniques to ensure ‘Zero Defect’ chips
• Collaborate with SME’s and key leaders in architecture, systems, emulation, SoC design, software, physical design, and IP teams developing key technical networks to influence overall design improvements and verification methodologies
• Responsible for developing detailed Technical SoC verification execution plans, progress reports and tracking milestones, managing technical risks, and providing mitigations to meet schedule quality and costs commitments. Communicate across technical teas as well as provide executive level presentations
• Complete ownership for SoC verification quality sign-offs ensuring all deliverables for team hand-offs.
• Drive best in class verification methodologies collaborating with global internal and external SME’s and developing adoption and compliance processes. Including, driving key innovation strategies which significantly impact efficiency and quality for overall R&D and ROI
• Bachelor’s or master’s degree in electronics engineering.
• 14+ years of experience in SoC Verification domains and have working knowledge of industry standard EDA toolkits.
• Experience in Microcontroller and Microprocessor architecture & Interconnect
• Experience in protocols like AHB/AXI, Memory (ROM, RAM, Flash, MRAM) and memory controllers.
• Advanced knowledge of Verilog, System Verilog, C/C++, Shell.
• Good knowledge in scripting like Perl, TCL or Python is a plus
• Proven experience in testbench design and development using UVM methodology for IP/Subsystem and SOC.