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Microchip’s Communications Business Unit (CBU) is a premier supplier of 100Gbps+ Optical Networking and Connectivity Solutions for Telecom and Hyperscale Data Center Networks.
Our state-of-the-art devices power high-bandwidth, cloud-based applications including streaming services, social media platforms, and video conferencing worldwide.
The CBU Product Development team drives the full semiconductor R&D lifecycle—from initial concept, design, and implementation to embedded software integration, system validation lab testing, and mass-market production release.
Working with the latest tools and methodologies in advanced process nodes, our experienced team delivers industry-leading network devices.
We are seeking a Principal Engineer to join the CBU Product Development team.
In this role, you will lead the digital design, DFT, physical implementation, and static timing analysis (STA) of integrated circuits at both the block and top chip levels.
Working alongside our implementation team on advanced technology nodes, you will drive RTL-to-pre-layout netlist generation and own STA signoff across multiple macros, subsystems, and full-chip designs using industry-standard Cadence and Synopsys synthesis suites.
Microchip’s Communications Business Unit (CBU) is a premier supplier of 100Gbps+ Optical Networking and Connectivity Solutions for Telecom and Hyperscale Data Center Networks. Our state-of-the-art devices power high-bandwidth, cloud-based applications including streaming services, social media platforms, and video conferencing worldwide.
The CBU Product Development team drives the full semiconductor R&D lifecycle—from initial concept, design, and implementation to embedded software integration, system validation lab testing, and mass-market production release. Working with the latest tools and methodologies in advanced process nodes, our experienced team delivers industry-leading network devices.
We are seeking a Principal Engineer to join the CBU Product Development team. In this role, you will lead the digital design, DFT, physical implementation, and static timing analysis (STA) of integrated circuits at both the block and top chip levels.
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Working alongside our implementation team on advanced technology nodes, you will drive RTL-to-pre-layout netlist generation and own STA signoff across multiple macros, subsystems, and full-chip designs using industry-standard Cadence and Synopsys synthesis suites.
Responsibilities:
Responsible to develop macro constraints (Synthesis, STA & Layout), ram generations, flow configuration for High-speed complex macro s and Subsystems.
Responsible for STA sign off for all levels of design hierarchy for multiple modes and multiple corners (MMMC)
Responsible to develop/understand flow and methodology for doing RTL Synthesis.
Ability to pick up new flows, learn on the job and influence QOR is a must.
Co-work with RTL and DFT engineers and interact with project teams to ensure the right constraints/deliverables are in place.
Ensure the Quality of deliverables pre/post netlists (CLP, LEC, In-house tool checks)
Close interactions with APR team to ensure that floorplanning /macro placements/quality of deliverables are in the right direction.
To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.
A leading provider of smart, connected, and secure embedded control solutions.
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Senior · 10+ years experience
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