Principal Digital Verification Engineer (Memory Interface IP- HBM/DDR/LPDDR)

Deliver Interface IP that powers memory subsystems in AI accelerators, mobile SoCs, and high-performance computing platforms used across the industry

Reduce post-silicon bugs and customer escalations by catching issues early through rigorous verification and coverage-driven testing

Shape the verification methodology and standards that the team will use for the next generation of memory IP products

Accelerate project schedules by building reusable verification components that cut bring-up time on future designs

Raise the technical bar across the verification team by mentoring engineers and sharing hard-won lessons from complex bring-ups

Contribute to the quality and reputation of Synopsys IP, which directly affects customer trust and product adoption

Help define what "done" means for verification, ensuring that coverage, corner cases, and compliance are never compromised under schedule pressure

Bachelor's or Master's in Electrical Engineering or Computer Engineering with 8 to 10+ years of hands-on ASIC or SoC verification experience

Proven track record verifying Interface IP protocols such as HBM, DDR, LPDDR, or AMBA in production-level designs

Strong proficiency in SystemVerilog and UVM, including building testbenches, writing assertions, and developing verification IP

Deep understanding of digital design concepts, timing, protocol compliance, and memory subsystem architecture

Experience using simulation tools such as VCS, ModelSim, Xcelium, or equivalent in a regression and debug workflow

Demonstrated ability to drive functional coverage closure and deliver fully verified IP on schedule

Experience with HBM2, HBM3, DDR4, DDR5, LPDDR4, or LPDDR5 is a strong plus

You can look at a failing test and quickly narrow down whether it is a testbench issue, a design bug, or a timing problem without burning a day in the debugger

You push back when a test plan is too shallow or a coverage model is missing a critical scenario, and you do it in a way that helps the team get better

You can explain a complex protocol violation to a design engineer in two sentences without losing the technical nuance

You are comfortable working across time zones and teams, coordinating with architects in one region and design engineers in another without losing momentum

You take ownership of the verification closure process and do not wait for someone else to tell you what needs to be done next

You mentor junior engineers by showing them how to think through a problem, not just how to fix the immediate issue in front of them

You will be part of a highly skilled and motivated verification team focused on delivering cutting-edge Interface IP solutions. The team is dedicated to maintaining the highest standards of quality and performance, working collaboratively to tackle complex verification challenges. You will have the opportunity to work alongside industry experts and contribute to the development of next generation technologies.