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Lead methodology enablement, project alignment, centralized CAD flow management, and Physical Design support for the Silicon organization. The role will own and advance Physical Verification and PERC methodologies, partnering closely with design teams to improve productivity, quality, and execution consistency Develop, maintain, and support Physical Verification (PV) flows across all Silicon projects, spanning early design (shift‐left) through final signoff, including DRC, LVS, ERC, antenna, and advanced checks. Own PV methodology, including guidelines, checklists, milestone definitions, and waiver strategies, ensuring consistent and predictable execution across programs and nodes. Partner closely with Physical Design teams to: Enable early PV runs Debug complex DRC/LVS/ERC/PERC issues Identify systemic design or flow gaps and drive fixes to closure. Lead resolution of PV‐related flow and design issues, including tool stability, runtime scalability, deck integration, waiver correctness, and cross‐tool debug. Drive cross‐functional alignment with CAD, Technology, and external EDA partners to communicate PV requirements, influence roadmap priorities, and unblock execution at critical project milestones. Support PDK and node enablement activities, ensuring PV flows are validated, production‐ready, and aligned with foundry decks and internal signoff criteria across multiple technology variants. Lead the development and deployment of AI-enabled agents to automate and optimize Physical Verification (PV) and PERC workflows across the Silicon organization. Contribute to PV activities, including training material, documentation, onboarding labs, and continuous improvement of automation and debug infrastructure. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. BS + 15 years / MS + 13 years of relevant experience in Physical Verification, Physical Design, or CAD methodology roles. Hands‐on experience with Physical Verification checks, including DRC, LVS, ERC, Antenna, Metal Fill, etc. Proficiency with industry‐standard PV tools, such as Calibre. Scripting skills in at least one language (TCL, Python, Perl, or equivalent) for flow automation, debug, and data analysis. Ability to debug complex, cross‐domain issues, reason about root cause (design vs flow vs tool), and drive issues to closure across teams.
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