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Principal ASIC verification Engineer

Nokia
USA
Full-time
Senior
Hybrid
Discovered 2 weeks ago
cplusplusmatlab
Free

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Responsibilities

  • Model the circuit blocks and mixed-signal IPs, including but not limited to high-speed ADCs, DACs, CTLE, FFE, and PLLs, to work with the architect and designers to achieve the optimal system-level performance.
  • Perform the functional verification and timing analysis on the IPs and the blocks.
  • Work with the digital verification team to generate an adequate interface to ensure the robustness of the design.
  • - Model the circuit blocks and mixed-signal IPs, including but not limited to high-speed ADCs, DACs, CTLE, FFE, and PLLs, to work with the architect and designers to achieve the optimal system-level performance. - Perform the functional verification and timing analysis on the IPs and the blocks. - Work with the digital verification team to generate an adequate interface to ensure the robustness of the design.

Qualifications

  • Mandatory Knowledge/Skills/Abilities:
  • Have prominent tracking record in modeling analog/mixed-signal IPs, including but limited to SERDES, optical links, and wireless transmission systems.
  • Hands-on in modeling and simulating with System-Verilog (WREAL), Verilog-AMS, and/or C, C++.
  • Have a decent understanding in CMOS analog / mixed-signal design.
  • Preferred Knowledge/Skill/Abilities:
  • Able to create IBIS-AMI model.
  • Can code in System-Verilog (WREAL).
  • Able perform.LIB generation
  • Fluent in verbal and written communications;
  • Independently resolves issues and conquer design challenges;
  • Self-motivated and detail-oriented;
  • Has the knowledge of (optical) communication theories and Matlab coding.
  • Education and Experience Requirements:
  • Principal Design Engineer: M.S. in E.E. with 12+ years’ experience, or Ph.D. in E.E. with 8+ years’ experience
  • Mandatory Knowledge/Skills/Abilities: - Have prominent tracking record in modeling analog/mixed-signal IPs, including but limited to SERDES, optical links, and wireless transmission systems. - Hands-on in modeling and simulating with System-Verilog (WREAL), Verilog-AMS, and/or C, C++. - Have a decent understanding in CMOS analog / mixed-signal design. Preferred Knowledge/Skill/Abilities: - Able to create IBIS-AMI model. - Can code in System-Verilog (WREAL). - Able perform.LIB generation - Fluent in verbal and written communications; - Independently resolves issues and conquer design challenges; - Self-motivated and detail-oriented; - Has the knowledge of (optical) communication theories and Matlab coding. Education and Experience Requirements: - Principal Design Engineer: M.S. in E.E. with 12+ years’ experience, or Ph.D. in E.E. with 8+ years’ experience

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