Principal ASIC Design Engineer (Starshield)

RESPONSIBILITIES:

• Design digital ASICs and/or FPGAs for Starshield projects.
• Evaluate architectural trade-offs based on features, performance requirements and system limitations. Derive specifications for the subsystems and circuits, and work with modem/DSP and RFIC engineers to partition functions between hardware and software domains.
• Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
• Work closely with verification team to ensure all aspects of the design are covered and verified.
• Provide timing constraints for those IPs and support the physical implementation team (synthesis, timing closure, formality check).
• Participate in silicon bring-up and validation. Assist in the development of automated test lab equipment for lab measurements.
• BASIC QUALIFICATIONS:
• Bachelor’s degree in electrical engineering, computer engineering, or computer science.
• 8+ years of experience in RTL implementation and/or FPGA/ASIC development.
• PREFERRED SKILLS AND EXPERIENCE:
• Experience solving problems including clock domain crossings and power optimization.
• Experience developing complex ASICs.
• Experience with multicore CPU subsystem design.
• Experience with standard bus protocols (e.g. AXI, AHB, etc.).
• Experience with embedded processors.
• Experience with high speed and low power design techniques.
• Scripting skills (Python, TCL etc.).
• Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado, Altera Quartus II).
• Ability to work in a dynamic environment with changing needs and requirements.
• Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis.
• Enjoy being challenged and learning new skills.
• ADDITIONAL REQUIREMENTS: