Principal Analog Design engineer

Summary: Analog Designer with 12 to 18 years of experience in High speed design which includes Automotive Ethernet and SerDes blocks.

Will be part of Ehernet PHY and switch Product development team.

Job qualification:

• 12+ years of Analog experience in high speed design of ethernet/Serdes blocks

Transistor level design knowledge and experience of standard analog building blocks including Bandgap references, current references, OPAMP, LDO, receiver front-end blocks PGA, CTLE and such for ultra-low noise performance in CMOS processes.

Design experience in Ethernet/SerDes is a plus.

Good knowledge on EMC/ESD concepts

• Experience with relevant CAD tools (including Cadence Virtuoso, SPICE, etc.).

on solving Product level EMC/ESD issues

Proficient with using analog circuit design EDA tools such as Cadence ADE.

Have knowledge of basic transistor models (CMOS).

with Analog circuit characterization/validation, Yield improvement, ATE characterization etc.

on Multi-gig ethernet is a plus.

Job responsibilities:

• Transistor level design knowledge and experience of standard analog building blocks including Bandgap references, current references, OPAMP, LDO, receiver front-end blocks PGA, CTLE and such for ultra-low noise performance in CMOS Finfet processes