Power Integrity Engineer

Responsibilities

• Support the design and analysis of Power Delivery Networks (PDNs) for digital and analog SoC domains, including path from voltage regulators to on-chip decoupling capacitors.
• Assist in modeling regulator characteristics such as switching ripple and transient response to aid in component selection (controllers, passives, etc.).
• Use commercial simulation tools (e.g., 2.5D EM solvers) to extract PCB and package impedance profiles and help generate N-port models.
• Perform basic time-domain and frequency-domain simulations to evaluate supply rail behavior and identify potential issues such as voltage droop or overshoot.
• Conduct lab measurements to validate power integrity design, including use of programmable loads and oscilloscopes to capture transient response.
• Work closely with hardware designers, layout engineers, and system integrators to implement PDN design improvements and validate results.
• Participate in design reviews and contribute to documentation of analysis results, test procedures, and design recommendations.
• Help monitor and review PDN constraints during layout and provide feedback based on simulation or measurement data.
• Support senior engineers in system-level tradeoff studies and architectural evaluations related to power integrity.

Qualifications