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MatX's mission is to make the world’s best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability.
We are looking for a Power Architect to drive power architecture and cross-stack power tradeoffs for our next-generation products.
MatX is vertically integrated, which means important power decisions can happen anywhere: architecture, RTL, physical design, platform. This role connects those layers. You will work with domain owners as true technical counterparts, understand their constraints, and help MatX make better power decisions as the design moves from idea through deployment. You’re not expected to own every implementation domain, but you are expected to understand enough across the stack to surface tradeoffs, build shared models, and drive aligned decisions.
Own MatX’s shared power architecture framework for server-class AI accelerators.
Define power budgets, models, targets, and tradeoff methods.
Build and correlate estimation frameworks that connect architecture intent to implementation reality.
Partner with architecture, RTL, DV, PD, and platform teams.
Surface and track cross-functional power tradeoffs across the product lifecycle.
Drive decisions across power, performance, area, timing, voltage, thermal, reliability, schedule, and deployability.
Translate power assumptions and data into actionable guidance for implementation teams.
Help define power-control features, throttling, and telemetry.
Deep experience in power architecture, power modeling, power methodology, or power-performance analysis for complex chips.
Ability to reason across architecture, RTL, PD, firmware, platform, and thermal constraints and tradeoffs.
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Experience building early models to influence direction and later models for correlation.
Strong analytical skills for modeling, automation, and data analysis.
Clear judgment in ambiguous cross-functional decisions.
Credibility with senior technical counterparts across multiple disciplines.
Ability to communicate tradeoffs and drive alignment.
Experience with AI accelerators, GPUs, datacenter CPUs, networking silicon, or other server-class chips.
Experience with ML workloads and perf/Watt analysis.
Experience correlating architectural models to RTL, PD, silicon, or platform measurements.
AI semiconductor company designing high-throughput chips for large language models and frontier AI labs.
Visit company websiteJobs and hiring trendsUSD 120000-600000 yearly / year
Full-time
Senior
Hybrid
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