greenhouse
PLL Design Engineer
Celero Communications, Inc.
Irvine, USA
Full-time
Senior · 5+ years experience
Onsite
USD 150000-250000 yearly / year
Discovered 3 weeks ago
Cadence VirtuosoEMXHFSSMATLAB
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Role Overview
Are you a PLL Design Engineer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI?
We are looking for a High-Speed CMOS PLL Analog Design Engineer –who is excited to join a fast-growing Start-Up Company with a key role for expert in clocking circuits for next generation optical transceivers, high-speed SerDes, and ADC/DAC systems
Preferred Location - On-Site at one of our offices: San Jose, CA, or Irvine, CA HQ
Alternate Locations - Vancouver, British Columbia; Ottawa, Ontario
Candidate will have the opportunity to architect and design PLLs for next generation transceivers.
Key Skills for This Role
Cadence VirtuosoEMXHFSSMATLAB
Full Job Posting
About the job
Are you a PLL Design Engineer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI? We are looking for a High-Speed CMOS PLL Analog Design Engineer –who is excited to join a fast-growing Start-Up Company with a key role for expert in clocking circuits for next generation optical transceivers, high-speed SerDes, and ADC/DAC systems
Preferred Location - On-Site at one of our offices: San Jose, CA, or Irvine, CA HQ
Alternate Locations - Vancouver, British Columbia; Ottawa, Ontario
Candidate will have the opportunity to architect and design PLLs for next generation transceivers.
What You Will Do
- Understand trade-offs between different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency range
- Architect, design and simulate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters) at transistor level using tools like Cadence Virtuoso and Spectre
- Address challenges in advanced node technologies, such as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization and device-level noise optimization
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