Package Design Principal Engineer

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Marvell’s Central Engineering team is seeking a talented High-speed IC package development engineer to contribute to the development of advanced microelectronic packages.

The engineer will be responsible for driving microelectronic package development from concept through tapeout, working with package architects and technical leads to select appropriate technologies and ensure manufacturability, performance, reliability, and cost compliance.

Key responsibilities include developing C4 and BGA ball maps optimized for SI/PI and layout efficiency; planning and validating netlist mappings across dies, interposers, and substrates; and defining die placement, padstacks, net assignments, and package ‑ level connectivity.

The engineer will create and maintain Package Requirement Documents (PRDs) detailing die arrangements, stackups, and design constraints.

13-16 years of related professional experience.

Previous experience developing netlists and schematics for large, complex packages.

Previous experience developing C4 and BGA ball maps for high ‑ pin ‑ count designs.

Proficiency with design tools Cadence OrbitIO / Integrity System Planner (ISP) or equivalent