NAND BM IP RTL Design Engineer

Role and Responsibilities

Samsung Semiconductor India Research (SSIR) is looking for a bright RTL Design Engineer who will be responsible for performing concept and specification study of Samsung Memory (Flash, DRAM).

Providing high quality RTL design in terms of performance, emulation compatibility and area utilization. Writing detailed design specification and micro architecture documents. Memory team, SSIR Bangalore plays a key role in maintaining this leadership by continuous innovation and applying it to a real life products. We provide the opportunities for you to share and build up your knowledge and expertise, and collaborate to drive innovation forward. At Samsung, you will witness your ideas come to life in new products and solutions that shape the future.

Experience: 6+ years

RTL design using Verilog or System Verilog. Strong RTL coding practices.

Design of complex state machines, data paths and arbitration.

Exposure to emulation and emulation compatible RTL design.

Ability to verify functionality with Unit level TB.

Modelling and performance simulation.

Prior experience on memory design is a plus.

Knowledge on area optimization techniques on Emulation platform would be an asset.

Strong Problem solving and RTL debugging skills

Writing detailed design specification and micro architecture documents.

Experience in FPGA based prototypes development

Individual should be self-driven, adaptable, flexible, creative, and capable of working independently.

The candidate needs to be solution-orientated, quality-driven and focused on timely deliverables

Skills and Qualifications