Memory Layout Design Engineer, Staff

Your layouts will directly enable memory IP that ships in high-volume semiconductor products across automotive, mobile, AI, and data center applications

You will reduce design cycle time by improving layout automation and methodology, allowing the team to take on more projects with higher quality

Your ability to close complex DRC and LVS issues independently will unblock project milestones and keep compiler development on schedule

You will raise the technical bar for the team by mentoring junior designers and establishing layout standards that scale across technology nodes

Your collaboration with circuit and CAD teams will surface layout-driven insights that influence architecture and tool development decisions

You will help Synopsys deliver memory IP that meets the most demanding area, performance, power, and reliability requirements from leading semiconductor companies

Your work on technology migrations will position the memory IP portfolio for next-generation nodes and maintain Synopsys leadership in the market

Bachelor's or Master's degree in Electronics, VLSI, Microelectronics, or a related technical field

8 to 10 years of hands-on experience in custom memory layout design, specifically SRAM, Register Files, ROM, or memory compiler development

Strong proficiency with custom layout tools such as Cadence Virtuoso or equivalent platforms

Demonstrated expertise in DRC/LVS closure, device matching and symmetry, and analog/custom layout techniques

Deep understanding of CMOS layout fundamentals, memory architecture, and FinFET technology nodes

Experience with parasitic extraction and physical verification flows, and the ability to interpret and act on results

Familiarity with scripting in Tcl, Perl, or Python for layout automation is a strong plus

You can debug a complex LVS mismatch by tracing through netlists, schematics, and layout views without needing someone to walk you through it

You know when to optimize for area and when to prioritize matching or performance, and you can explain the trade-off to a circuit designer in a way that moves the decision forward

You review a junior engineer's layout and give feedback that is specific, actionable, and grounded in what will actually cause problems downstream

You work across teams with circuit designers, methodology engineers, and CAD without losing sight of what you are trying to deliver or when it needs to be done

You stay current on process technology changes and layout challenges that come with new nodes, and you bring that knowledge into your daily work

You take ownership of your projects and deliver milestones with limited supervision, raising issues early when dependencies or risks emerge

Your recruiter will share more about the team structure and mission during the interview process.