Lead verification Engineer - high speed protocol

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

Lead Verification Engineer – Data Center Networking (AMD)

This is an exciting opportunity to join AMD’s Data Center Networking Technology Solutions group as a Lead Verification Engineer , contributing to next‑generation data center networking solutions that power AI training and inference at scale. In this role, you will lead verification for IP or subsystem or system‑level designs within high‑performance networking domains. You will collaborate closely with architects and designers while driving verification strategy, methodology, and execution.

Key Responsibilities

As a Lead RTL Verification Engineer, you will independently drive verification architecture, methodology, and execution for Data Center Networking IPs and systems:

Technical Responsibilities

Work experience on high‑speed and complex protocols such as PCIe, Ethernet, CXL, RoCE / NVMe ‑ oF, etc.

Architect, design, and develop testbench infrastructure and verification environments for complex networking IP and systems.

Interpret product specifications and derive scalable and reusable verification architectures.

Create comprehensive verification plans , test plans , coverage plans , and assertions .

Build block‑level and multi‑block verification environments using System Verilog/UVM .

Develop reusable verification components, sequences, and methodologies to ensure robust verification quality.