Lead Power and Performance Attainment Engineer

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

AMD’s Datacenter Performance Group is seeking a senior Power & Performance Architect for driving the Power Constrained Performance of our industry-leading AI/ML/HPC GPUs. The role will involve owning the Perf@Power attainment of a leading generation of our Instinct accelerators, providing cross-functional leadership for a virtual team that drives all aspects of Perf@Power attainment, including pre-Si modeling, post-Si correlation, workload analysis, setting PPA targets and driving attainment, power/perf roll-ups and reporting, methodology innovations and development. Being passionate about performance and power efficiency, influence without authority and excellent communication skills are key ingredients for success in this role.

KEY RESPONSIBILITIES: • Own power-constrained performance modeling, projections, implementation target setting and attainment tracking from Concept-exit (pre-si) to Product launch (post-si) for AMD Instinct AI/ML/HPC accelerators • Work with business unit and product architecture to define product configurations, capabilities and P&P targets • Cross functionally lead P&P attainment by working with various engineering functions including SOC architecture, System Design, IP Design, Circuit Design, Foundry team, CAD, Physical Design, Software, Power Management, Post-si validation • Roll-up Power/Performance readouts, present in executive forums, motivate cross-functional teams on power efficiency improvements • Mentor junior engineers and develop skillsets and methodologies in the team for important PPA domains like Power Modeling at various stages of SoC development, Cdyn/Leakage/STA/Area trade-offs and attainment, Silicon Power/Performance debug, Post Si calibration of models, Work-load power analysis KEY QUALIFICATIONS: • Background in Computer Architecture, Processor/Accelerator development • Experience in Power/Performance projections, modeling and optimization at SoC or System level • Familiarity with digital logic physical design and power management techniques (clock gating, power gating, V-F curves, p-states, on-die voltage regulation, clock integrity, etc..) • Familiarity with post-silicon power/performance debug, model correlation • Fluency in communicating with various engineering teams, business leads and executive management • Knowledge of DL/ML/LLM/MoE workloads will be a bonus EDUCATION: • Bachelor’s or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or related