Lead MTS DFT at Rambus — Bengaluru, IND | Base Career

Full Job Posting

Overview

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead MTS DFT Engineer to join our Interconnect team in Bengaluru.

Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

As a Lead MTS DFT Engineer, the candidate will be reporting to Manager DFT Engineering and is a Full-Time position.

As a Lead MTS DFT Engineer, the candidate will be responsible for design, implementation, and verification of all aspects of DFT on complex SoCs at advanced process technology nodes.

Responsibilities

Developing DFT test plan for IP blocks and SoC level
Identifying and implementing RTL changes for DFT
Performing DFT IP insertion for scan and memory BIST
Developing timing constraints for test mode timing closure
Scan and ATPG for different fault models
Boundary scan, ACJTAG, IEEE 1500 implementation and verification
IEEE1687 (iJTAG) for functional manufacturing tests
Executing and debugging RTL and gate level simulations with and without timing annotation
Supporting post silicon vector bring up and debug
Developing/Improving DFT process and methodologies

B.E./B.Tech/M.E/M.Tech
8+ years of experience with B.E./B.Tech or 6+ years with M.E./M.Tech
Experience with SoC DFT architectures and concepts
Experience with industry standard EDA Tools such as Mentor Tessent, Cadence Modus, or Synopsys TestMAX
Experience with logic simulators
Experience with RTL lint tools
Experience with scan insertion, ATPG, coverage analysis and debugging fault coverage
Experience with memory BIST insertion
Experience running and debugging ATPG and MBIST gate level simulations with timing annotation
Programming in Perl/Tcl/Python or other scripting languages is desired
Experience with post silicon validation, debug and support on ATE are desired
Excellent analytical and communication skills

With 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications.

From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future.

Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program and gym membership.

Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.

Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures.

If you need assistance or an accommodation due to a disability, you may let us know in the application.

For more information about Rambus, visit rambus.com.

For additional information on life at Rambus and our current openings, check out rambus.com/careers/ .

Lead MTS DFT

Job Fit Check

Role Overview

Key Skills for This Role

Full Job Posting

Overview

Responsibilities

Apply for this job in 1 click

More jobs at Rambus

Lead Facilities Administrator

MTS Verification Engineering

Lead Digital Design Engineer, # 1048 (Agoura Hills, CA)

Analog Design Engineer, #1217 (San Jose, CA)

Sr Principal Logic Design Engineer, #1221 (San Jose, CA)

Principal Analog/Mixed-Signal Design Engineer (PE Analog Engineering) #1218

Director/Sr Manager - Silicon IP Sales

Principal Field Applications Engineer