Lead Design Engineer

B.S. in Electrical Engineering or a related field with 3+ years of relevant experience, or an M.S. with 1+ years.

Strong analog CMOS, noise, jitter, feedback, signal-integrity, and data-converter fundamentals.

Hands-on transistor-level design experience with high-speed SerDes circuits.

Excellent command of Cadence Virtuoso, Spectre , Spectre RF, ADE, parasitic extraction, and mixed-signal verification flows.

Strong analytical, communication, collaboration, and engineering judgment.

Preferred Qualifications

Experience with PAM4/NRZ SerDes, advanced CMOS or FinFET technologies, and standards such as Ethernet, PCIe, or CXL.

MATLAB or C for architecture development; SystemVerilog or Verilog-A for functional modeling; and Perl or Python for automation.

Experience using AI-assisted engineering tools responsibly for design exploration, verification, debugging, documentation, and workflow automation.

Custom analog layout experience is a plus.

Lab characterization experience is a plus, along with experience taking mixed-signal IP from architecture through tapeout and silicon validation.

Success in This Role

The ideal candidate combines strong circuit intuition, disciplined verification, ownership, and clear communication to deliver reliable, power-efficient SerDes solutions.