Layout Design, Sr Staff Engineer

Your layouts will directly enable high-speed SerDes IP that powers data center, automotive, and AI applications shipping in volume production

Clean, first-pass layout quality from your work reduces costly respin cycles and accelerates time to market for Synopsys IP customers

Your deep understanding of FinFET effects and advanced node challenges will help the team navigate complex process technology transitions

Collaboration with circuit designers ensures that performance targets are met in silicon, not just in simulation

Your floorplanning and verification rigor will set the standard for layout quality across the analog and mixed signal IP group

Automation scripts you develop will multiply the productivity of the entire layout team

Your ability to work independently means the team can scale and take on more complex IP development without bottlenecks

Bachelor's or Master's degree in Electronics Engineering or Electrical Engineering

6+ years of hands-on experience in analog and mixed signal custom IC layout, with specific exposure to high-speed analog circuits

Proven experience with Custom Designer or Cadence Virtuoso for layout design

Strong working knowledge of Calibre, ICV, and STAR-RXCT for DRC, LVS, and parasitic extraction

Solid understanding of CMOS and FinFET layout techniques, deep submicron effects, and mitigation strategies

Experience with layout verification flow including LEF generation, top-level integration, EM/IR analysis, and DFM considerations

Familiarity with ESD and latchup layout design rules and how to apply them in real designs is a strong plus

You can look at a schematic and immediately start thinking about device matching, shielding strategy, and how parasitics will affect circuit performance

When a DRC violation shows up at 4pm before tapeout, you do not panic, you methodically trace it back, understand the root cause, and fix it without breaking LVS

You communicate clearly with circuit designers, explaining layout tradeoffs in terms they care about without needing three meetings to get alignment

Ownership comes naturally to you, if you say a block is ready for integration, the team knows it has been checked, verified, and will not come back with surprises

You are comfortable working independently on your day-to-day tasks but know when to pull in a colleague or escalate a risk before it becomes a problem

Scripting for layout automation is something you see as a force multiplier, not a distraction, and you look for opportunities to eliminate repetitive manual work

You will join the Analog and Mixed Signal IP group, working with a team of custom layout design engineers focused on SerDes and high-speed analog IP blocks. This is a collaborative team where layout engineers work closely with circuit designers to deliver production-quality IP that ships to customers globally.