Layout ASIC Engineer

As a Layout Engineer in the Client Optics Group (COG) Engineering Team, you will collaborate with a multidisciplinary team including analog/mixed-signal circuit designers, digital designers, verification engineers, package engineers, process technologists, CAD specialists, reliability experts, and post-silicon validation teams.

You will partner with architects and designers during concept and planning phases, contribute to layout execution during design, work with signoff teams prior to tapeout, and support debug efforts post-silicon when layout-related issues arise. This role is a great opportunity to grow while helping deliver high-speed electrical IPs such as SerDes, PAM4 interfaces, D2D PHY, clocking subsystems, and control logic.

Bachelor’s degree in Electrical Engineering or related field (Master’s preferred)

4-6 years of experience in custom IC layout for analog, mixed-signal, and high-speed designs

Solid technical skills with an interest in growing into layout leadership; strong foundation in matching, symmetry, shielding, parasitic control, thermal management, and signal integrity

Good knowledge of device-level layout techniques (common-centroid, interdigitation, guard rings, isolation structures)

Proficiency with industry-standard tools such as Cadence Virtuoso and Calibre (or equivalent)

Understanding of DRC, LVS, ERC, parasitic extraction, EM/IR analysis, and physical signoff flows

Familiarity with ASIC/SoC tapeout processes is preferred

Experience with scripting (Python, Perl, or TCL) for layout automation is a plus

Comfortable working in Linux environments

Excellent analytical, problem-solving, communication, and teamwork skills

Demonstrated ability to contribute effectively and grow as a technical leader in a fast-paced environment

Ability to work as a team player with cross-functional teams spread across geo-locations.

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