IP Verification Engineer

Responsibilities

• THE ROLE: As a Senior ASIC Verification Engineer, you will help bring to life cutting-edge FPGA, ASICs for variety of target customers. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, PD teams, and product engineers to achieve first pass silicon success. THE PERSON: You have a passion for modern, complex IP architectures, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBLITIES: - Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified for PCIe CXL based IP's - Develop test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases - Code IP or SS level UVM based testbenches, verification components - monitors, scoreboard, checkers - Build the directed and random verification tests - Run regressions, debug test failures towards ensuring high design functional, perfor