IP Design Verification Engineer

General Summary:

We are looking to hire a strong DV engineer to work on verification for the Infra IP team

Create DV infrastructure for verification

Integrate VIP's

Create and execute test plans, debug failures, write assertions, close code and functional coverage

Ensure high quality verification

Working with all stakeholders to ensure program success

Minimum Qualifications

Bachelor's degree in Engineering, Electronics, Information Systems, Computer Science, or related field.

4+ years Hardware Engineering experience or related work experience.

Preferred Qualifications

Strong Debug, UVM, System Verilog coding skills

• Understanding Specs and Standards and developing relevant test plans

• Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved

• Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into failures and understand what is happening

• Thorough understanding of Digital design concepts

• Thorough understanding dv methodologies and tools

• Good understanding of LPDRR/PCIe/CXL protocols is an added advantage

Minimum Qualifications:

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