IP Design Verification Engineer

Role and Responsibilities

Design & maintain UVM‑based verification environments for high‑speed serial IP blocks (e.g.,56G/112G/224G Gbps SERDES, PCIe Gen4/5, Ethernet MAC/PHY,) and security IP (AES/SHA engines, ECC, secure‑boot, root‑of‑trust).

Develop comprehensive test plans and coverage models that capture protocol corner cases, timing jitter, eye‑diagram constraints, and security threat scenarios.

Create reusable UVM components (agents, drivers, monitors, scoreboards, and protocol checkers) that can be shared across multiple serial and security projects.

Implement constrained‑random traffic generators with data‑pattern, error‑injection, and latency‑stress capabilities to validate link reliability and security robustness.

Integrate formal verification and assertion‑based checking (SVA) to capture protocol violations, key‑exchange errors, and timing violations early in the flow.

Run and maintain regression suites on industry‑standard simulators (VCS, Xcelium, Questa) and CI pipelines; monitor functional coverage, protocol coverage, and security‑feature coverage.

Collaborate closely with design, architecture, and security teams to refine specifications, resolve bugs, and drive design for testability (DfT) and low‑power considerations.

Mentor junior verification engineers, enforce coding standards, and contribute to the IPD verification methodology library.

Participate in design reviews, risk assessments, and compliance verification (e.g., PCI‑SIG, IEEE Ethernet, NIST crypto standards).