IC Test Process/ Test Cell Development Manager

Design and develop test cell configuration, docking/undocking handlers and probers, including hardware change kits for NPI programs & production ramp-ups.

Assist with test floor tool setup, ensure smooth transition from NPI to production by buying off new hardware and clarifying constraints

Handler and Prober change Kits development and setup and manage teams

Architect and deploy automated test cells for wafer sort and final test.

Familiar with all the testers (Advantest (93K), Teradyne Ultra Flex/J750, Eagle ETS, Nextest, Advantest), Handler/Probers Good Knowledge working on Handler (Hon Precision, Delta Matrix), probers (TEL, Accretes) and identifying the Handler & Prober for the NPI devices, sockets for the devices, burn-in equipment’s and process.

Ensure scalability, repeatability, and robustness of test cell designs.

Integrate test cells with OSAT production lines, balancing throughput, cost, and reliability.

Oversee qualification and release of new test platforms and equipment.

Continuous Improvement - Suggest DOE/project actions to improve uptime & yield

Collaboration & Coordination - Engage with NPI, planning, engineering, spare-stock teams

Hands-on troubleshooting skills for handlers, probers, sockets, probe cards, and load boards.

Assist in managing handler docking, qualification of multiple change kits, and maintaining documentation for hardware swaps during ramp-up and product transitions.

Localize the Change Kits.

Identify recurring machine faults or inefficiencies and propose improvement projects or DOE initiatives in collaboration with Engineering and NPI teams

Assist in roll-out of hardware improvements, process standardization, and updates to checklists.

Lead cross-functional teams of test engineers, technicians, and operators.

Train staff on wafer probe and final test methodologies, equipment, and best practices.

Act as the primary liaison between OSAT customers and internal teams for test-equipment’s related issues.

Define and optimize wafer probe and final test processes for semiconductor devices.

Collaborate with design, product, and test engineering teams to ensure test coverage, yield, and throughput.

Drive continuous improvement initiatives using Lean/Six Sigma practices.

Monitor KPIs such as yield, defect detection rate, cycle time, and equipment utilization.

Ensure compliance with industry standards (JEDEC, ISO, IPC).

Support customer audits and technical reviews.

Minimum 8–12 years in semiconductor test engineering within OSAT, IDM, or ATE vendor environments; at least 4 years in a leadership role.