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IC Layout Engineer
Silicon Technologies Inc.
Midvale, USA
Full-time
Mid
Onsite
Discovered 1 weeks ago
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Create DRC/LVS/DFM-clean library cells for the ADONIS Correct-by-Architecture methodology.
Work on advanced process nodes and radiation-hardened layouts.
Experience
with Cadence Virtuoso required.
About Silicon Technologies Inc.
Semiconductors8 employeesFounded 2009
Designs and licenses analog and mixed-signal semiconductor IP.
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