IC Layout Engineer

• Conduct detailed physical design and layout analysis of AI and datacenter hardware, including GPUs, ASICs, CPUs, custom accelerators, high-speed I/O, memory subsystems, and their packaging
• Perform digital and analog floorplan analysis: identify functional blocks, partitioning strategy, hierarchy, power and clock distribution, and I/O placement from die-level imagery
• Assess standard-cell library choices, cell utilization, placement density, and area/timing/power optimization strategies across designs and process nodes
• Analyze analog/mixed-signal layout regions (SerDes, PLLs, PHYs, power management) and interpret matching, isolation, and routing choices
• Drive end-to-end teardown and characterization; operate the analytical toolchain and direct more specialized work as needed
• Identify competitive advantages, disadvantages, and generational changes in physical design, packaging, and system-level decisions
• Apply Design Technology Co-Optimization (DTCO) and System Technology Co-Optimization (STCO) reasoning to interpret layout trade-offs and process-design interactions
• Co-author technical research published by SemiAnalysis, combining physical observation, cross-industry context, and argument all in your words
• Contribute to the growth and expansion of the lab's capabilities and output; bring your unique skills to a strong and expansive team

• We are hiring at all experience levels: 2+ years of industry experience in IC layout, physical design, place-and-route, custom/analog layout, or closely equivalent is preferred, but all exceptional candidates are encouraged to apply
• Genuine exposure to leading-edge parts
• Strong functional knowledge of digital and/or analog physical design flows (floorplanning, placement, CTS, routing, and signoff) on advanced process nodes
• Working understanding of standard-cell architectures, cell utilization metrics, and area/power/performance optimization techniques
• Strong functional knowledge of AI and datacenter hardware architecture (GPUs, CPUs, accelerators)
• Direct experience in physical or electrical failure analysis, fault isolation, device debug, or related physical root-cause work, or strong aptitude to build it
• Understanding of Design Technology Co-Optimization (DTCO) principles
• Hands-on experience with, or strong aptitude for, semiconductor sample preparation and analytical tools such as precision polishing, FIB, SEM, and related electron-beam, X-ray, and compositional methods

• Experience with industry P&R and custom layout tools (e.g., Innovus, Fusion Compiler, Virtuoso) and reading GDS/OASIS-level detail
• Analog/mixed-signal layout expertise, including matching, shielding, guard rings, ESD, and high-speed interconnect layout
• Product design or manufacturing R&D in advanced packaging (2.5D / 3D, high-speed interconnects, hybrid bonding)
• Broad understanding of advanced manufacturing across CMOS logic, memory, and emerging technologies
• Interpreting micrographs and electrical measurements to infer design and process characteristics, e.g., identifying cell libraries, track heights, fin/nanosheet configurations, and metal stack usage from imagery
• Comfort developing plans for physical and electrical FA toolchains
• Python for data analysis and engineering tasks (image analysis, layout metrics extraction, automation)
• Strong professional network of experts
• Statistical and process-control literacy

• Deepen expertise in next-generation AI hardware physical design, including custom accelerators, chiplet-based designs, and heterogeneous compute systems
• Expand capabilities in advanced packaging and interconnect technologies (e.g., 2.5D/3D integration, HBM, optical interconnects) and their layout- and system-level implications
• Develop stronger cross-layer understanding, from device physics, standard-cell design, and manufacturing processes through floorplan, system architecture, and workload optimization
• Build proficiency in data-driven layout analysis, including automated die-image analysis, utilization and density benchmarking, and performance modeling using Python and related tools
• Strengthen collaboration with research, manufacturing, and market teams to translate physical design findings into high-impact strategic insights
• Enhance external engagement through interaction with industry experts, conference participation, and contribution to thought leadership
• Progress toward a senior physical design analyst or subject matter expert role with influence over research direction, technical coverage, and industry perspective

• Layout fluency: floorplans, standard-cell fabrics, memory macros, and advanced I/O are native language for you
• Cross-industry context: you place any physical design choice against vendor and competitor history without reaching for a reference
• Physical intuition, or willingness to build it fast: you know what is real and what is artifact
• Written argument: your technical writing holds up under expert scrutiny
• Curiosity and ownership: you're drawn to investigate; you ship and close your own loops
• Agency: you deliver on your responsibilities and support others in theirs. You treat everyone you work with as a peer and leave concepts of hierarchy at the door.

80% onsite in Hillsboro, OR.

US work authorization required; no visa sponsorship.

Competitive compensation commensurate with experience!

SemiAnalysis LLC participates in the E-Verify program to confirm the employment eligibility of all newly hired employees.

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• E-Verify Poster: https://www.everify.gov/sites/default/files/everify/posters/EVerifyParticipationPoster.pdf
• Right to Work Poster: https://www.justice.gov/crt/case-document/file/1133936/dl?inline=