IC Layout Design

In this position, you will work closely with design engineering to complete the layout and verification of high-performance mixed-signal CMOS Integrated Circuits using Cadence Virtuoso XL and Mentor's Calibre tools, and work with circuit engineers to generate topological layouts to ensure optimal circuit performance.

• Solving layout design issues and applying proactive intervention
• Proactively work with design engineers to achieve efficient circuit performance
• Design analog & mixed-signal layouts
• Understand device matching techniques
• Understand signal conditioning/protection techniques
• Strong collaboration skills, including written and verbal communication
• Outstanding layout planning and integration skills
• Experience in routing at the block level and chip top-level using assisted/automated tools