HW/SW Codesign Engineer

Phinity is building prompt-to-silicon: the agent infrastructure that enables AI agents to design, verify, optimize, and ultimately tape out chips. By 2028, any company will be able to specify a set of requirements for a chip and Phinity will deliver them a GDS file in weeks, not years.

Today, chip development requires large teams, fragmented tools, and multi-year development cycles. We are building a closed-loop system in which models can reason about hardware, use engineering tools, learn from verification feedback, and perform increasingly consequential parts of the chip-development process.

We work with leading frontier AI labs and are building a small team with deep experience across AI research, silicon architecture, design, and verification. Our long-term goal is autonomous tapeout, making custom silicon accessible enough to accelerate technological progress at breakneck speed.

The HW/SW Codesign Engineer role is for an engineer who works at the boundary between silicon and software and wants to define how a new chip actually gets used, heavily using AI to speed up development. Some example responsibilities include:

Design the hardware/software interface for edge compute chips: the programming model, command processors, memory movement, and runtime-visible scheduling that let software drive the hardware

Build and own the firmware, drivers, and runtime for chip bring-up and expose its capabilities to software

Make co-design tradeoffs across the boundary, deciding what belongs in hardware, firmware, or software, and own the technical bar for how they fit together

Validate the subsystem across emulation, FPGA, and bring-up, making sure software-visible behavior matches intent