HDL Technical Team Lead

We are looking for an HDL Technical Team Lead to guide and elevate our FPGA/HDL development efforts across multiple advanced RF programs.

This role is ideal for a senior HDL engineer who enjoys technical leadership, system-level thinking, and influencing how teams build, without direct people management responsibilities.

You will serve as the technical lead across 3-4 concurrent programs, providing architectural guidance, ensuring consistency and reuse across designs, and helping teams make sound engineering tradeoffs.

While approximately 50% of your time will be hands-on (including specialty tooling and targeted development), most of the role is strategic and coordination-focused – driving technical direction, alignment, and execution across projects.

This is a high-impact role for someone who enjoys leading through expertise, mentoring by example, and shaping how systems come together on a scale.

• Serve as the technical lead for HDL development across multiple concurrent programs
• Guide system-level HDL architecture and ensure designs align with program requirements and long-term platform strategy
• Identify opportunities to reuse architecture, IP, and tooling across projects to improve efficiency and consistency
• Lead technical planning, design reviews, and cross-team alignment — ensuring teams move quickly without sacrificing quality
• Spend ~50% of your time on specialty tooling, targeted HDL development, and complex problem-solving
• Collaborate closely with RF, embedded software, and hardware teams to ensure seamless system integration
• Support and mentor HDL engineers through technical guidance, design feedback, and best-practice development — without direct people management
• Own and influence design documentation, simulation strategy, verification approach, and integration readiness
• Evaluate architectural trade-offs, interfaces, and timing constraints across systems and programs
• Support hardware bring-up and integration efforts in Linux-based environments
• Evaluate architectural trade-offs, interfaces, and timing constraints across systems and programs