Hardware Validation and Debug Engineer - DDR

Graphcore is a globally recognised leader in Artificial Intelligence computing systems.

The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies.

We are expending our labs in Bristol which will play a central role in Graphcore's work building the future of AI computing.

We are looking for a Validation and Debug engineer to work with Architecture, Silicon Engineering, Hardware Engineering and the Firmware team to help create and execute the bring-up and debug of our cutting-edge system platforms.

As such you will need to develop a detailed understanding of our silicon and platform products.

will be to create and execute Validation and Debug plans of our silicon devices and platforms in systems to show that they will operate correctly over all conditions in the final product.

This Validation will also involve debugging of hardware and firmware.

You will concentrate on mainly manual testing of systems in the lab with the aid of some automation.

• Perform Validation and Debug for new hardware platforms.
• Debug PCB, power, signal integrity, and interface issues.
• Validate and debug high-speed memory interfaces and slow speed interfaces
• LPDDR5-9600 memory interfaces
• SPI/I2C/I3C/UART
• Support LPDDR5-9600 initialization, training, timing optimization, margin analysis, and stability validation.
• Analyse DDR timing margins, signal integrity, eye diagrams, and training behaviour.
• Identify root causes and drive corrective actions across hardware and firmware domains.