Hardware Engineering, Architect-17965

Job Description and Requirements

• We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: A seasoned engineer with over 15 years of experience in DDR/HBM SIPI engineering. You possess a deep understanding of high-speed interface signaling operations, including s-parameters, channel loss, crosstalk, equalization techniques, jitter, and power delivery modeling. Your expertise in signal and power integrity analysis methods, such as eye diagram construction through statistical modeling, return loss, impedance matching, and resonant system analysis, is unmatched. You are proficient in using HFSS and Ansys tools, HSPICE, Raptor, and ADS. You excel at generating and communicating results, findings, conclusions, and recommendations within a design team and to external customers. Your knowledge in board-level construction and on-chip IO design operation allows you to work seamlessly across multi-site teams, communicating ideas, understanding problems, and finding solutions to create leading-edge designs. As a team player, you communicate clearly and efficiently, leading issues to full closure independently. Your ability to track industry developments through activities at standards committees and memory vendor roadmaps ensures that you stay ahead of the curve in technological advancements. What You’ll Be Doing: * Perform interconnect assessments using the latest modeling techniques to predict channel data rates and signal margins. * Assess strategies for system performance optimization, including signal margins, power, and FFE, DFE, and CTLE equalization techniques. * Assess power delivery systems to optimize power integrity for supply stability and jitter minimization. * Document findings in reports and design guidelines. * Communicate results and insights to design teams to improve PHY design. * Communicate results and recommendations to customers to enable them to optimize their system performance. * Interact with design teams and customers to refine and apply signal and power analysis methods to refine strategies and address problems. * Understand Synopsys’ DDR and HBM PHY roadmap and create strategies for improved performance. * Track industry developments through activities at standards committees and through memory vendor roadmaps.