FPGA Designer/Verification Engineer

Responsibilities

• Full FPGA development cycle involving architecture definition, verification strategy definition, RTL/Testbench coding, simulation, timing analysis, synthesis, place & route and on-board testing.
• Validate that system meets design requirement: Write test plans for RTL validation. Develop verification collateral (such as BFMs, behavioral checkers, coverage monitors, or score-boards). Define and run system simulation models, and find and implement corrective measures for failing RTL tests. Analyze and use results to modify testing.
• Build and maintains tools and processes associated with FPGA development.
• Participate in project planning activities.
• Understand product requirements, participate in software/FPGA partitioning and implement/validate FPGA functional blocks.
• Work with other engineers on a team to integrate FPGA designs on projects that include hardware and software design components
• Minimum of 5 years of pertinent experience.
• Strong VHDL/Verilog design and coding skills for synthesizable FPGA designs.
• SystemVerilog and OOP coding skills for verification testbench development. UVM knowledge is an asset.
• Good understanding of FPGA design considerations including synchronous/asynchronous/CDC timing requirements and FPGA resource utilization.
• Experience with 3rd-party VHDL/Verilog IP.
• Experience with scripting languages for tool automation and FPGA validation. TCL and Python knowledge is an asset.
• Ethernet expertise is an asset. Knowledge of ASIC development methodology is a plus
• Excellent written and oral communication skills, including the ability to produce clear, concise documentation.
• Passionate and self-motivated with the ability to learn quickly and independently.
• Team player capable to interact efficiently within multi-disciplinary engineering team.
• Pragmatic approach to problem solving.
• “Can-Do” attitude to overcome any kind of challenges.
• Ability to take full ownership of his task and project.
• Bilingual (French and English).