FPGA Design Verification and validation Engineer

Role overview

Key responsibilities

• Plan and execute end-to-end processing system solutions, including Vivado IP configuration through software execution for customer use cases.
• Collaborate with marketing, architects, hardware engineers, verification teams, and firmware engineers to define requirements.
• Work with cross-site stakeholders to drive requirements and deliverables within agreed scope and timelines.
• Develop processing IP solutions for AMD AECG FPGA, SoC, and ACAP platforms.
• Target solutions for bare-metal and operating-system-hosted environments.

Preferred experience

• Verilog or SystemVerilog coding and simulation experience.
• Understanding of FPGA fundamentals, AMD Xilinx or AECG FPGAs, timing constraints, static timing analysis, and timing closure.
• Knowledge of system-level architecture, including AXI, bridges, memory controllers, PCIe, Ethernet, or high-speed serial connectivity, is advantageous.
• Understanding of processing systems, boot processes, and I/O peripherals.