Formal Verification Engineer, Staff

General Summary:

We are seeking a highly motivated Formal Verification Engineer with 6-8 yeas of experience to join our GCAD Formal team. The ideal candidate will have strong formal verification fundamentals, hands-on experience with formal tools, excellent analytical and scripting skills, and the ability to drive innovative verification methodologies. This role provides the opportunity to collaborate across global architecture, design, and systems teams to influence and strengthen verification sign‑off quality.

Minimum Qualifications:

Drive formal verification of complex design blocks using advanced Formal Apps and robust convergence strategies to achieve exhaustive and high‑confidence sign‑off.

Collaborate with worldwide architecture, design, and systems teams to achieve verification goals.

Review and refine formal setups, proofs, constraints, and abstractions with design/DV teams.

Engage with EDA vendors and evaluate advanced DV methodologies to improve sign‑off quality.

Develop automation scripts (Python preferred) to enhance efficiency and scalability of FV flows.

Analyze challenging formal problems and propose effective verification strategies.

Low power formal methodology

6+ years of hands-on experience in Formal Verification.

Strong understanding of formal concepts, proof strategies, and abstraction techniques.

Proficiency with formal tools (Jasper, VC Formal, Questa Formal, etc.).

Working knowledge of property-based FV (SVA ) is a plus.

Excellent scripting skills (Python strongly preferred).

Strong analytical and problem‑solving abilities.

Clear communication skills and ability to collaborate with global teams.

A strong willingness to learn, innovate, and deliver high‑quality results.

Low‑power knowledge is a plus (e.g., power‑aware verification concepts, UPF/CPF, isolation/retention, power/clock gating, power‑aware apps, and basic power‑intent debugging).