Formal Verification

TCS IAE is redefining the future of industry by embedding intelligence across engineering, manufacturing, asset, and service value chains.

Powered by AI, connected ecosystems, and autonomous operations, it transforms insights into action—creating self-optimizing, resilient, and intelligent enterprises at scale.

By seamlessly converging the physical and digital worlds, TCS IAE is enabling a new era of AI-first enterprises where systems continuously learn, adapt, and evolve—driving measurable outcomes and shaping how industries operate for the future.

Role: Formal Verification Engineer (RTL to Netlist / Netlist to Netlist)

· Perform Netlist-to-Netlist equivalence across ECO, DFT, low-power, and PnR iterations

· Handle clock-gating, scan, and DFT-related equivalence challenges

· Collaborate with cross-functional teams for signoff readiness

· Formal Verification: Synopsys Formality, Cadence Conformal (LEC / Low Power)

· Low Power: UPF-aware formal verification

· Understanding of synthesis, STA, and physical transformations

· Scripting: Tcl (mandatory), Shell / Python (preferred)