ENGR II, PRODUCT; PROD&TEST

Responsibilities

• ATE (T2K, ETS364, 93K), HW design, TP development, debug, data analysis and presentation.
• Primary responsibilities: Define product DFT and test requirements Pre-PG including: a) DfT-max Requirements for a new product b) translate PRD / MRDs into PTS / SCMs / PRPs for ATE test-plan definition c) design ATE HW for lowest cost solution (max multi-site, lowest pin-mux) for Si bring-up and validation Post-Si bring-up and validation of all functional and test features. This includes extensive debug that will require good knowledge of IC design and semiconductor physics, with ability to clearly isolate and root-cause issues to design margins and/or sensitivies to wafer-fab process and parametric parameters. Execute design-of-experiments with process window corner lot to establish spec compliance of each product across full wafer-fab process window. Execute qualification cycles for Si and package to automotive, industrial, and commercial standards (as per the primary product market) During these various stages of Post-Silicon validation, you will interact with various cross-functional teams such as Design, DfT, Design Validation, Program Management, QRE/CQE, and Bench Characterization and Apps development teams Will actively own or be part of a team that owns ATE Test Solutions, including HW design, socket design, ATE Resource Allocation, Board Schematic, Layout, and Diagnostic code Will own product from bring-up to RTM (~12-14mo) and also own all the Product Entitlement goals and critical metrics for a successful ramp
• Define product DFT and test requirements Pre-PG including: a) DfT-max Requirements for a new product b) translate PRD / MRDs into PTS / SCMs / PRPs for ATE test-plan definition c) design ATE HW for lowest cost solution (max multi-site, lowest pin-mux) for Si bring-up and validation
• Post-Si bring-up and validation of all functional and test features. This includes extensive debug that will require good knowledge of IC design and semiconductor physics, with ability to clearly isolate and root-cause issues to design margins and/or sensitivies to wafer-fab process and parametric parameters.
• Execute design-of-experiments with process window corner lot to establish spec compliance of each product across full wafer-fab process window.
• Execute qualification cycles for Si and package to automotive, industrial, and commercial standards (as per the primary product market)