Digital Verification Engineer

At Nexthop AI, the correctness of our digital logic is non-negotiable — a single functional escape in an FPGA or ASIC can compromise an entire switching platform once it ships.

We are looking for a Digital Verification Engineer to own the verification environments and test suites that prove our digital subsystems behave exactly as designed.

Sitting within the Hardware Design organization, you'll work shoulder-to-shoulder with RTL designers and firmware engineers to catch bugs in simulation — long before they reach silicon, a board, or a customer's rack.

• Own the testbench: Design, build, and maintain the verification environments for our digital subsystems — from block level through full-chip / subsystem integration — for both FPGA and ASIC targets.
• Reusable methodology: Establish and evolve reusable verification components (drivers, monitors, scoreboards, checkers) so new blocks plug into a consistent, maintainable framework instead of one-off testbenches.
• Reference modeling: Develop behavioral / reference models where needed to independently predict expected DUT behavior and catch discrepancies automatically.

• Test suites: Author directed and constrained-random tests that exercise functional modes, corner cases, error injection, and reset / clock-domain behavior.
• Coverage-driven closure: Define functional and code-coverage goals and drive them to closure — identifying coverage holes and writing the stimulus to fill them.
• Assertions: Embed assertions (SVA) to catch protocol and interface violations at the source, close to where they occur.