Digital Design Verification Engineer, Staff

ASIC design verification experience including coding in Verilog/SystemVerilog

An applied understanding of UVM and verification techniques

Experience with constrained-random verification in SystemVerilog and UVM

Formal Verification and Power-aware verification techniques

Tools/languages: Verilog/System Verilog, Python, Perl, C/C++, GNU Make, EDA tools

Working knowledge of scripting and the Linux/Unix environment

Proven problem solving and analytical skills

Proven effective communication and organizational skills

Experience delivering multiple parallel programs on schedule

Strong initiative and independently capable of driving tasks to completion

Technical leadership skills to own new initiatives end-to-end

Experience with Ethernet, PCIe, SerDes PHY, DSP, and mixed-signal IP is highly desirable

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