Digital Design Engineer (Mid-Senior Level)

Verification leadership: Define and execute verification strategies using SystemVerilog and cocotb.

Develop constrained-random testbenches, close functional and code coverage, and triage simulation failures efficiently.

Timing closure: Drive STA and timing constraint development (SDC/XDC), identify critical paths, and work with synthesis and P&R flows to close timing on complex, multi-clock designs.

Lab bring-up & debug: Lead or actively participate in hardware validation.

From JTAG bring-up and FPGA prototype debug through to silicon characterisation using oscilloscopes, logic analyzers, and custom test frameworks.

Technical mentorship: Review the work of junior engineers, establish coding standards, and contribute to continuous improvement of team processes and tooling.

Cross-functional collaboration: Interface with RF, analogue, and firmware teams to define interfaces, agree on integration strategies, and resolve system-level issues.

Must-Have Qualifications Experience: 5–10 years of industry experience in digital IC or FPGA design, with a track record of shipping real silicon or production FPGA systems.

HDL expertise: Strong, production-proven proficiency in SystemVerilog and/or VHDL, synthesizable RTL, parameterised design, and structured coding for reuse and review.

Digital design depth: Expert-level understanding of synchronous design principles, multi-clock domain management, CDC strategies, reset topologies, metastability hardening, and pipeline design.

Verification competence Timing & implementation: Working knowledge of STA, timing exceptions, false paths, and constraint authoring; experience with FPGA implementation flows or ASIC synthesis.

Scripting & automation: Proficient in Python and/or Tcl for build automation, regressions, and flow scripting.

Comfortable in a Linux-based development environment with Git.

Communication: Able to produce thorough design specifications, lead design reviews, and communicate trade-offs clearly to both engineering and management stakeholders.

Nice-to-Have Experience with high-speed serial interfaces (PCIe, Ethernet, DDR) or RF/mmWave digital back-end design.

Familiarity with formal verification methods (model checking, equivalence checking).

Exposure to ASIC physical design flows: place-and-route (Genus and Innovus), DRC/LVS, sign-off (Voltus, Tempus), ATPG test pattern generation (Modus).

C/C++ for embedded co-development, firmware bring-up, or hardware/software interface definition.