DFT Design Engineer

Knowledge of DFT techniques such as JTAG/IEEE standards, SSN, Scan and ATPG, memory BIST/repair or Logic BIST

Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential.

Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations

Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl)

Familiar with Verilog design language, Verilog simulator and waveform debugging tools

Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus.

Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. is a plus

Strong problem-solving skills.

Team player with strong communication skills.

Bachelor’s or Master’s degree in electrical/Electronic Engineering with 8+Yrs

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Benefits offered are described: AMD benefits at a glance .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.