Design Verification Manager

Minimum requirements

• Education: Bachelor’s or Master’s degree in EE/EC/EI/CS, or related specializations.
• Experience: A minimum of 8-12 years in relevant fields.

Preferred Skillset

• Experience in C-based System-on-Chip (SoC) design verification (DV), with exposure to firmware verification and deep understanding of UVM/SystemVerilog, Specman, GLS/PAGLS/UPF based verification, post-silicon verification, etc.
• Proficient in scripting languages such as Perl and Python, and knowledgeable in AI/ML-based DV.
• In-depth understanding of various standard protocols, including AHB, CAN, I2C, SPI, UART, USB.
• Work experience in a C-based environment involving ARM systems, particularly with power-aware simulations, is a significant advantage.
• Strong grasp of digital design fundamentals, computer organization and architecture, and bus protocols.
• Excellent debugging skills with Verilog and VHDL designs.
• Solid problem-solving abilities.
• Familiarity with Cadence tools (such as Xcelium, vManager, Formal JG applications, and safety simulators) or similar tools and DV flows.
• Demonstrate excellent verbal and written communication skills, enabling the development of strong relationships and seamless interaction with key internal and external stakeholders.
• Proven ability to manage, lead, and collaborate with cross-functional teams while taking the initiative to drive projects forward.
• Familiarity with functional safety and cybersecurity processes
• Proactively improve daily operations by keeping up with the latest technical trends and actively participating in both internal and external technology forums and conferences.
• Demonstrate strong interpersonal and analytical skills to effectively address complex problems and navigate organizational challenges.
• Quickly adapt to new systems and processes while managing time effectively to ensure on-time delivery.

Company