Design Verification Engineer — Memory Subsystem

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 3–10 years of experience in ASIC, SoC, IP, or subsystem design verification.
• Strong hands-on experience with: Verilog SystemVerilog UVM SystemVerilog Assertions
• Verilog
• SystemVerilog
• UVM
• SystemVerilog Assertions
• Experience developing and debugging reusable UVM-based verification environments.
• Proficiency in developing UVM components such as sequences, drivers, monitors, scoreboards, agents, and functional coverage models.
• Experience with constrained-random verification and coverage-driven verification methodologies.
• Experience writing assertions for protocol compliance, temporal behavior, interface checking, and functional correctness.
• Strong understanding of digital design and verification fundamentals, including clocking, reset behavior, synchronous and asynchronous logic, and multi-clock-domain designs.
• Experience with simulation-based verification, waveform analysis, regression execution, and failure debug.
• Strong analytical, problem-solving, communication, and collaboration skills.

• Experience verifying LPDDR, DDR, DDR PHY, HBM, custom memory interfaces.
• Familiarity with JEDEC memory specifications and memory-protocol requirements.
• Understanding of memory-controller, memory-subsystem, and PHY architecture.
• Familiarity with integrating and configuring industry-standard verification IP.
• Experience working with commercial or internally developed memory models.
• Experience with power-aware simulation using UPF.
• Knowledge of standard interfaces such as AXI, APB, AHB, DFI, or similar protocols.
• Experience with formal verification or assertion-based verification methodologies.
• Experience verifying high-performance, low-power, or multi-clock-domain designs.
• Experience with performance verification, including bandwidth, latency, throughput, efficiency, QoS, and stress testing of memory subsystems.
• Familiarity with hardware/software co-verification or system-level validation.
• Experience with memory training, initialization, refresh, power-management, frequency-switching, calibration, or error-handling scenarios.

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The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted.

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