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Design Engineering Manager
Cadence
Bengaluru, IND
Full-time
Mid-Senior
Onsite
Discovered 1 weeks ago
Physical layer electrical validationHigh-speed SERDES protocolsOscilloscopesNetwork analyzersBit error rate testers (BERT)Test planning
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Physical layer electrical validationHigh-speed SERDES protocolsOscilloscopes
Role Overview
The role is in the Post Silicon Physical Layer Electrical Validation team in Cadence Design Systems Bangalore.
The manager leads pre-silicon validation infrastructure and post-silicon validation for high-speed SERDES test chips.
Key Skills for This Role
Physical layer electrical validationHigh-speed SERDES protocolsOscilloscopesNetwork analyzersBit error rate testers (BERT)Test planning
Full Job Posting
About Cadence
Cadence provides software, hardware, and intellectual property for electronic design across chips, boards, and systems.
The company serves markets including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial, and health.
Job Summary
The role is in the Post Silicon Physical Layer Electrical Validation team in Cadence Design Systems Bangalore.
The manager leads pre-silicon validation infrastructure and post-silicon validation for high-speed SERDES test chips.
Core Responsibilities
- Design hardware and software architectures for test chips, including test PCBs, controlling FPGA platforms, and LabVIEW or Python automation.
- Define test plans for rigorous testing against physical-layer electrical specifications.
- Implement validation tests and generate high-quality reports from test results.
Minimum Qualifications
- 6–10 years of post-silicon physical-layer electrical validation experience with a BTech, or 4–8 years with an MTech.
- Deep validation experience with at least one high-speed SERDES protocol, such as PCIe, USB, DP, Ethernet, SRIO, JESD204, or DDRIO.
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