Chip Design Engineer

Physical design is where AI-driven chip design gets graded: every placement, clock tree, routing, and optimization our systems produce must ultimately converge to signoff-clean GDSII in an advanced node. To close the loop between our AI and real silicon, we need an engineer who knows every step of the flow cold, from synthesis through tapeout, and who has personally fought complex blocks to closure at an advanced node. Your expertise becomes the ground truth our self-improving systems learn from and are measured against.

You will participate in developing the architecture of Ricursive's physical design flow end to end, both top-down (chip-level planning, partitioning, budgeting, hierarchical signoff) and bottom-up (block construction and closure feeding full-chip assembly), and you will pair that flow with AI tooling, ours and the industry's, to make each iteration faster than the last. This is a small and early team, so the methodology and infrastructure are still being defined; you will define them.