ASIC Physical Design & Implementation Lead

• 12+years of professional experience in physical design, preferably with high performance designs.
• Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications.
• Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
• Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery
• Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation
• Versatility with scripts to automate design flow.
• Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams
• Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm
• Excellent physical design and timing background.
• Good understanding of computer organization/architecture is preferred.
• Strong analytical/problem solving skills and pronounced attention to details.

BS or MS degree in in Electrical Engineering or Computer Science. 12+years of experience in physical design role leading to an understanding of RTL to GDS development.

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Benefits offered are described: AMD benefits at a glance .

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This posting is for an existing vacancy.