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Key skills for this role
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with formal and design verification.
Experience with SystemVerilog or Verilog.
Experience working with one or more formal verification tools (e.g., Jasper, VC Formal, Questa Formal, 360-DV).
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
6 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based Integrated Circuits (ICs) and chips.
Experience with scripting languages.
Excellent communication and collaboration skills.
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