ASIC Engineering Technical Leader

You will take on a technical leadership role within the Test Development Engineering team, responsible for architecting, developing, and deploying Automated Test Equipment (ATE) solutions for modern, highly complex ASICs and SoCs. You will own the end-to-end test development lifecycle from pre-silicon DFT engagement to post-silicon bring-up and high-volume manufacturing (HVM) release. As a senior technical driver, your responsibilities will include: • Test Architecture & Development: Architect, write, and debug complex ATE test programs for wafer sort and final test • Silicon Bring-Up: Lead first-silicon ATE bring-up, characterization, and validation of complex networking processors and multi-die packages. • DFT Collaboration: Partner closely with Design for Test (DFT) and ASIC design teams during the pre-silicon phase to define testability requirements, evaluate test coverage, and simulate test vectors (SCAN, MBIST, JTAG, High-Speed I/O). • Yield & Test Time Optimization: Drive pivotal initiatives for Test Time Reduction (TTR) and yield optimization without compromising test coverage or product quality. • Manufacturing Deployment: Lead the seamless transfer and release of robust test programs to offshore assembly and test (OSAT) partners. Resolve complex test-related issues in high-volume manufacturing. • Mentorship & Leadership: Serve as a domain expert and technical escalation point. Mentor junior engineers and drive continuous improvement in test methodologies and automation. Who You'll Work With

You will collaborate with ASIC design / DFT teams in the Central Hardware Group, peer Product Development Engineers & Test Engineers in Silicon Operations and with Project Managements, Test engineering, Quality & Reliability, Supply Chain Planning. You will also work with Cisco’s manufacturing partners to triage any failures and manage the OSAT production test activities.

You are a highly analytical, self-directed test engineering expert with a deep understanding of ATE hardware and software. You excel in debugging complex silicon issues and have a proven track record of delivering robust test solutions for high-performance ASICs.

Minimum Qualifications: • Education & Experience: BSEE or MSEE in Electrical Engineering, Computer Engineering, or a related field, combined with 8-12+ years of direct experience in ATE test development. • ATE Expertise: Expert-level proficiency in developing test programs on advanced ATE platforms, specifically Advantest V93000 (SmarTest). • Programming Skills: Strong coding and scripting skills in C/C++, Python, and/or Perl for test program development and data automation. • Technical Knowledge: Deep understanding of semiconductor testing fundamentals, including DC/AC parametric testing, digital vector execution, and mixed-signal testing. • High-Speed I/O: Experience testing high-speed SerDes and familiarity with advanced packaging technologies (2.5D/3D, chiplets). • DFT Fluency: Strong working knowledge of DFT architectures (ATPG, Logic BIST, Memory BIST, Boundary Scan/JTAG). • Problem Solving: Exceptional debugging skills and experience using lab equipment (oscilloscopes, BERTs, logic analyzers) in conjunction with ATE. • Communication & Leadership: Excellent verbal and written communication skills, with the ability to lead cross-functional technical initiatives and present complex data to leadership.