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ASIC Engineering Analog Design Leader:ASIC Engineering Analog Design Leader | high-speed optical transceiver circuits (modulator drivers, TIAs, CDRs, PLLs, ADC/DAC) | 10+ years
Cisco
Bengaluru, IND
Full-time
Senior · 10+ years experience
Onsite
Discovered 3 weeks ago
Cadence VirtuosoCaliberPythonC
Free
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Participate in analog/mixed-signal design for Cisco's next generation silicon photonics driver integrated circuits for 100G/200G/400G per Lambda solutions.
Drive full-chip electrical specifications, circuit design, and verification test plans from concept through production, coordinating across electrical, optical, and product teams.
Author mixed-signal datapath designs including photonics modulator drivers, serializers, PLLs, TIAs and control circuits while optimizing for power, performance, testability, and cost.
Debug complex silicon and system-level issues during bring-up, and lab validation phases, driving yield enhancements and failure analysis.
Collaborate with architecture, digital, SI/PI and product teams on verification, design and testability strategies.
Minimum Qualifications
- Bachelors + 10 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of high-speed AMS design experience
- Demonstrated expertise in high-speed optical transceiver design (modulator drivers, TIA, CDR, PLLs, ADC/DAC) and proficiency with industry standard tools (Cadence Virtuoso, Spectre, Caliber)
- Strong skills in device physics, & circuit operations
- Proficiency in Python or C for design automation, scripting, and analytical tools
Preferred Qualifications
- Master’s or PhD degree in Electrical Engineering
- 8-10 years of hands-on analog/mixed signal circuit design experience
- Experience with silicon photonics driver ICs and direct-detect optical module architectures
- Good understanding of silicon photonics, optical subsystems
- Expertise in one or more high-speed PHYs, protocols and subsystems (SerDes 112Gbps/224Gbps PAM4, Ethernet, UCIE, clock and data recovery systems, PLLs, ADC/DAC circuits)
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