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ASIC Engineer, Physical Design

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Synopsys IC CompilerCadence InnovusPrimetime

Lead physical implementation of complex ASIC blocks or full chips, including floorplanning, placement, clock tree synthesis, routing, and signoff across advanced process nodes
Define and drive physical design methodology, flow development, and best practices across the physical design organization
Perform and own timing closure, including static timing analysis, timing constraint authoring, and multi-corner multi-mode signoff
Drive power integrity analysis and optimization, including IR drop, electromigration, and dynamic power reduction techniques
Collaborate with RTL design and architecture teams to provide physical design feedback on microarchitecture decisions, floorplan feasibility, and design-for-manufacturability
Partner with custom layout and circuit design teams to integrate analog and mixed-signal blocks into the digital physical implementation flow
Develop and maintain physical design scripts, automation flows, and runsets to improve team productivity and implementation quality
Conduct design rule check and layout versus schematic verification, resolving violations in coordination with foundry and design teams
Evaluate and qualify new EDA tools and process design kits, providing technical recommendations to improve physical implementation outcomes
Mentor other engineers on physical design techniques, flow improvements, and signoff methodology across the team

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
8+ years of experience in ASIC physical design, including hands-on ownership of full physical implementation flows from floorplanning through tapeout
8+ years of experience with industry-standard EDA tools for placement, routing, clock tree synthesis, and signoff (e.g., Synopsys IC Compiler, Cadence Innovus, Primetime, Calibre)
Experience with static timing analysis, timing constraint development, and multi-corner multi-mode closure at advanced process nodes (7nm or below)

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