{bc}
Apply
company_site

ASIC Engineer, Implementation

Meta
Bengaluru, IND
Full-time
Entry · 2+ years experience
Onsite
Discovered 1 weeks ago
SystemVerilogPythonTCLDesign CompilerSpyglassPrimeTime
Free

Job Fit Check

Base Career helps you apply smarter for this job.

?%
Ready to Scan

Key skills for this role

SystemVerilogPythonTCL
Smart Apply

Full Job Posting

Responsibilities

  • Run Logic/Physical Synthesis using advanced optimization techniques and generate an optimized Gate Level Netlist for Timing, Area, and Power
  • Debug the timing/area/congestion issues and work with RTL and physical designers to resolve them
  • Perform power estimation at RTL and gate level, and identify power reduction opportunities
  • Run Formal Verification checks between RTL and gate-level netlist, and debug the aborts, inconclusive, and logic equivalency failures
  • Perform RTL Lint and work with the designers to create waivers
  • Perform RTL DFT analysis and improve the DFT coverage for stuck-at faults
  • Develop timing constraints for RTL synthesis and PrimeTime-STA for the blocks and the top-level including SoC
  • Analyze the inter-block timing and come up with I/O budgets for the various partition blocks
  • Developing automation scripts and methodology for all FE tools including (Lint, CDC, RDC, Synthesis, STA, Power)
  • Work closely with the design engineers, DV engineers, emulation engineers in supporting them with the handoff tasks
  • Interact with Physical Design Engineers and provide them with timing/congestion feedback

Minimum Qualifications

  • 2+ years of experience as a Front-End Synthesis & Integration Engineer
  • Experience with RTL synthesis and design optimization for power, performance, and area
  • Knowledge of front-end and back-end ASIC tools
  • Experience with RTL design using SystemVerilog or other HDL
  • Experience managing multiple design releases and working with cross-functional teams to support and debug timing, area, and power issues
  • Experience with communicating across functional internal teams and vendors

Preferred Qualifications

  • Knowledge of Physical Design flow such as Floorplanning, CTS, Routing
  • Knowledge of STA signoff and understanding of AOCV, POCV
  • Good Understanding of Timing/physical libraries, SRAM Memories
  • Experience with EDA tools and scripting languages (Python, TCL) used to build tools and flows
  • Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools
  • Experience with low power techniques for reducing power
  • Experience in SOC Design Integration and Front-End Implementation

Apply for this job in 1 click

Skip the repetitive application forms

Install the Base Career Chrome Extension and autofill job applications across major job boards with your profile.

Sarah M.James T.Maya R.

Trusted by over 500,000 job seekers on Base Career

Start Free Today

More from this employer

More jobs at Meta

Product Manager, Agent Enablement

London, GBR

Discovered TodayFull-time

Technical Program Manager

Redmond, USA

Discovered TodayFull-time

NPI Operations Program Manager

Sunnyvale, USA

Discovered TodayFull-time

Project Manager, Verification Operations

Austin, USA

Discovered TodayFull-time

Sales Strategy and Planning Operations Lead, GBG Americas

Austin, USA

Discovered TodayFull-time

Product Designer

London, GBR

Discovered TodayFull-time

Logistics Operations Manager, Site Services

Temple, USA

Discovered TodayFull-time

Nanofabrication Engineer, Optical Systems

Redmond, USA

Discovered TodayFull-time