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ASIC Engineer, Design

Meta
Sunnyvale, USA
Full-time
Senior · 6+ years experience
Onsite
USD 146000-209000 yearly / year
Discovered 1 weeks ago
RTLSynthesisTiming ClosureFormal Verification MethodologySoC
Free

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RTLSynthesisTiming Closure
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Responsibilities

  • Develop micro-architecture, RTL coding, and design verification for complex IPs.
  • Work with architects to map algorithms onto the hardware and specify requirements for IP and subsystems integration.
  • Assist performance/power analysis of the design and help meet power and performance targets.
  • Collaborate with adjacent teams such as Verification, Physical Design, and Design-for-Test.
  • Drive IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leads.

Minimum Qualifications

  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 6+ years of experience as a Hardware Design Engineer for production silicon shipped in volume
  • Experience in digital design Microarchitecture, RTL coding, SoC integration and micro-architecture development
  • Demonstrated communication and collaboration skills

Preferred Qualifications

  • Master’s or PhD degree in Electrical Engineering, Computer Science or related areas
  • Experience in CPU, NOC, Memory, Die-to-die and Peripheral Subsystems
  • Experience with Synthesis, Timing Closure and Formal Verification Methodology
  • Experienced in managing SOC-level boot flow, Silicon Debug architectures and PLL/sequencing clocks and resets within SOC architectures

Compensation

  • $146,000/year - $209,000/year; Country: US; Bonus eligible; Equity eligible

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